Publication date: 15 October 2026
IBM and Siemens have begun a research collaboration aimed at moving IBM’s experimental “nanostack” transistor architecture closer to manufacturable technology. Announced on 14 October, the work will combine IBM’s device research with Siemens’ electronic-design automation, process simulation, lithography optimisation and manufacturing software.
The significance lies less in a new performance claim than in the transition the partnership is trying to make. Semiconductor laboratories regularly demonstrate structures that are difficult to reproduce economically in high-volume fabs. IBM says it has already shown that nanostack is viable at the device level; the next challenge is to build the design and manufacturing toolchain required for repeatable production.
Why stack transistors vertically?
Conventional chip progress has long depended on shrinking features and packing more transistors onto a flat surface. As physical limits and manufacturing complexity increase, the industry is looking upward as well as inward. IBM’s nanostack design vertically stacks and staggers nanosheet transistors, seeking to fit more computing elements into a given area and allow different material combinations in each layer.
IBM says its current 7-angstrom demonstration contains nearly 100 billion transistors in an area roughly the size of a fingernail. When the architecture was unveiled in June, Reuters reported IBM’s claim that it could deliver up to 50% higher performance or 70% greater energy efficiency than the company’s earlier 2-nanometre technology, as well as a 40% reduction in the area used by SRAM memory circuits. Those figures are company projections from research hardware, not results from commercial mass production.
The hard part is making a process repeatable
The new collaboration focuses on virtual models, simulation and lithography—the practical disciplines that help engineers predict how a complex design will behave before expensive wafers are fabricated. IBM and Siemens say they intend to model performance, optimise designs and identify fabrication problems earlier in the development cycle.
That approach reflects a wider change in advanced chipmaking. At leading-edge dimensions, transistor design, materials, manufacturing equipment and software can no longer be developed in isolation. A promising device architecture is only useful if design tools can represent it accurately, lithography can pattern it within acceptable tolerances, and factories can achieve viable yields.
Siemens’ role is therefore central rather than auxiliary. Electronic-design automation is the bridge between a physical concept and the enormous design complexity of a working processor. Better simulation does not guarantee commercial success, but it can reduce the number of costly physical iterations and expose manufacturing constraints before they become programme-ending problems.
A long road to commercial chips
The announcement does not include a production date, a manufacturing customer or evidence of high-volume yield. Those absences are important. The collaboration should be read as an effort to create the engineering foundation for future nanostack generations, not as the launch of a market-ready processor.
Even so, the direction is consequential. AI systems and other compute-intensive applications are increasing demand for performance and energy efficiency at a time when traditional scaling is becoming harder and more expensive. If vertically integrated transistor architectures can be designed and manufactured reliably, they could extend the industry’s ability to improve computing density without relying solely on two-dimensional shrinkage.
The real milestone to watch is not another laboratory density record. It is evidence that nanostack designs can be modelled, fabricated and repeated at acceptable yield and cost. By bringing manufacturing software into the research programme now, IBM and Siemens are addressing the part of semiconductor innovation that ultimately decides whether a striking prototype becomes an industrial platform.